|
Dimitris Gizopoulos Professor, University of Athens, Department of
Informatics & Telecommunications
IEEE Fellow (Class of 2013)
|
|
Contact
information: Mailing address: University of Athens, Department of
Informatics and Telecommunications
Panepistimiopolis, Ilissia, GR 157 84,
Athens, Greece (Office A36, 1st floor) Phone: +30 210 727 5145 Fax: +30 210 727 5214 Email: d g I z o p
|
|
I am Professor at the Department of
Informatics & Telecommunications (link)
of the National
& Kapodistrian University of Athens (link) in Greece where I am
leading the Computer Architecture Laboratory. My group’s research focuses on the area of Dependable and
Energy-Efficient Computer Architecture, and in particular
fault/error tolerance, design correctness validation and their relation to
performance and energy-efficiency for microprocessors and
microprocessor-based systems. I have introduced techniques for efficient
ISA-based error and bug detection in different microprocessor architectures
and test time optimization techniques for multithreaded and multicore
architectures. Currently, our research focuses on computing systems
reliability assessment at the microarchitecture level (for CPUs, GPUs and
other accelerators), the investigation of the voltage and frequency limits of
modern CPUs hardware for energy efficiency and performance boosting, and the
silicon debug/validation of complex microprocessor architectures. I received my engineering diploma from the Department of Computer
Engineering & Informatics of the University of Patras
and my PhD from the Department of Informatics & Telecommunications of the
National & Kapodistrian University of Athens.
Before joining the University of Athens, I worked at the Department of
Informatics of the University of Piraeus. Even before that, I worked as
post-doc fellow at the Institute of Informatics and Telecommunications of the
NCSR “Demokritos” and as research
engineer in the private sector. |
|
Group research
funded/supported by:
|
News 
New Special
Issue – Guest Editor for IEEE
Transactions on Sustainable Computing Special Issue “Beyond the Energy
& Performance Scaling Boundaries of Modern Computer Architectures” , Call
for Papers (link).
New
Editorial Service – Associate Editor for
IEEE Transactions on Sustainable Computing (T-SUSC), January 2017 –
present (link).
New Book - “Dependable
Multicore Architectures at Nanoscale”, M.Ottavi,
D.Gizopoulos, S.Pontarelli
(editors), Springer, July 2017 (link to Springer).
Keynote
Talk – “Microarchitecture Level Reliability
Assessment”, China Test Conference 2016, Nantong, China,
July 2016.
IBM
Faculty Award 2016 –Validation of
Cloud Computing Enabling Features: the Address Translation Mechanisms of a
High-Performance Microprocessor.
New
H2020 Project Starts (February 2016) – UniServer: Universal
Micro-Server Ecosystem by Exceeding the Energy and Performance Scaling
Boundaries (link to
project)
Funded Research Projects
UniServer [Universal
Micro-Server Ecosystem by Exceeding the Energy and Performance Scaling
Boundaries], H2020 (February 1, 2016 – January 31, 2019). 
CLERECO [Cross-Layer
Early Reliability Evaluation for the Computing cOntinuum], FP7 STREP (October
1, 2013 – November 30, 2016). 
– completed
HOLISTIC [Hardware and
Software Techniques for Multicore Processor Architectures Reliability
Enhancement], “Thales” research program, Ministry of
Education – completed
DIaSTEMA [Data-Intensive
Space Applications on Emerging Massively Parallel Processor Architectures:
Performance, Energy, and Dependability Opportunities], “Greek-China
Research Collaboration 2012-2015”, Ministry of Education – completed
AMD/UoA – unrestricted research grant on
“Hardware Faults in Performance Structures of
Microprocessors: Implications Analysis and Hybrid Online Detection and
Diagnosis Methods”.
Cisco/UoA – unrestricted research grant on
“Accelerated Online Detection of Functional and
Performance Errors in Complex Multiprocessor Chips”.
ABB/UoA – Smart
Diagnosis for Reliable and Safety Critical Microprocessor-Based systems
IBM
Research (IBM
Faculty Award 2016) –Validation of
Cloud Computing Enabling Features: the Address Translation Mechanisms of a
High-Performance Microprocessor
Networks
of Excellence
MEDIAN [manufacturable
and dependable multicore architectures
at nanoscale], ESF COST Action, member, Vice-Chair (link) – completed
HiPEAC [European Network of
Excellence on High Performance and Embedded Architecture and Compilation], FP7,
member (link)
Editorial Service
|
Member of
Editorial Boards: IEEE Transactions on Sustainable Computing, 2017
– present (link). IEEE Transactions on VLSI Systems, 2009 – 2015
(link). IEEE Transactions on Computers, 2007 – 2013 (link). IEEE Design & Test of Computers, 2002 –
2015 (link). Springer Journal of Electronic Testing: Theory and
Applications, 2006 – present (link). |
Special
Issues Guest Editor: IEEE Transactions on Sustainable Computing (early
2019) topic “Beyond the Energy & Performance
Scaling Boundaries of Modern Computer Architectures” (CFP link) IEEE Transactions on Device and Materials
Reliability (March 2017) topic “On-Line Testing and Robust
System Design” (guest
editorial) IEEE Transactions on Computers (January 2011) topic
“Dependable Computer Architecture” (guest
editorial). IEEE Transactions on VLSI Systems (April
2007) topic “Autonomous Silicon Validation and
Testing of Microprocessors and Microprocessor-Based Systems” (guest
editorial). IEEE Design & Test of Computers (May-June 2004)
topic “Design for Yield and Reliability” (guest
editorial). IEEE Communications Magazine (September 2003) topic
“Testing and Verification of
Communication System-on-Chip Devices” (guest
editorial). Springer Journal of Electronic Testing: Theory and
Applications, topic “Manufacturable and
Dependable Multicore Architectures at Nanoscale”. |
Publications/Citations
Full lists: DBLP Bibliography Google Scholar
Microsoft Academic Research
Some Publications Highlights
MICRO 2017 – “Harnessing Voltage Margins for Energy
Efficiency in Multicore CPUs”, G.Papadimitriou,
M.Kaliorakis, A.Chatzidimitriou,
D.Gizopoulos, P.Lawthers, S.Das, IEEE/ACM International Symposium on
Microarchitecture (MICRO 2017), Boston, MA, USA, October 2017 (PDF file).
ISCA 2017
– “MeRLiN: Exploiting Dynamic Instruction
Behavior for Fast and Accurate Microarchitecture Level Reliability
Assessment”, M.Kaliorakis, D.Gizopoulos,
R.Canal, A.Gonzalez,
ACM/IEEE International Symposium on Computer Architecture (ISCA
2017), Toronto, Canada, June 2017
DSN 2017
“RT Level vs. Microarchitecture Level Reliability Assessment: Case Study
on ARM Cortex-A9 CPU”, A.Chatzidimitriou, M.Kaliorakis, D.Gizopoulos, M.Iacaruso, M.Pipponzi, R.Mariani, S.Di Carlo, IEEE/IFIP
International Conference on Dependable Systems and Networks (DSN 2017), Denver,
CO, USA, June 2017.
ISPASS 2017 (poster)
– “Multi-faceted Microarchitecture Level Reliability Assessment of
Modern GPU Designs”, A.Vallero, S.Tselonis, S.Di Carlo, D.Gizopoulos, IEEE International Symposium on Performance
Analysis of Systems and Software (ISPASS),
2017 (poster).
VTS 2017 – “Performance-Aware Reliability Assessment of
Heterogeneous Chips”, A.Chatzidimitriou, M.Kaliorakis, S.Tselonis, D.Gizopoulos, IEEE VLSI Test Symposium (VTS 2017), Las Vegas, NV, USA, April, 2017.
IEEE TDMR
– “An Agile Post-Silicon Validation
Methodology for the Address Translation Mechanisms of Modern
Microprocessors", G.Papadimitriou, A.Chatzidimitriou, D.Gizopoulos, R.Morad, IEEE Transactions on Device and Materials
Reliability (IEEE TDMR), accepted for publication.
IJPP – “Hierarchical Synthesis of Quantum and Reversible
Architectures", A.Pavlidis, D,Gizopoulos,
Springer, International Journal of Parallel Programming (IJPP), vol. 44, no. 5, pp. 1028-1053, October 2016.
“Cross-Layer
System Reliability Assessment Against Hardware Faults”, A.Vallero, A.Savino, G.Politano, S.Di Carlo, A.Chatzidimitriou, S.Tselonis, M.Kaliorakis, D.Gizopoulos, M.Riera, R.Canal, A.Gonzalez, M.Kooli, A.Bosio, G.Di Natale, IEEE
International Test Conference (ITC 2016), November 2016.
“Unveiling Difficult Bugs in Address Translation Caching Arrays for
Effective Post-Silicon Validation”, G.Papadimitriou,
D.Gizopoulos, A.Chatzidimitriou,
T.Kolan, A.Koyfman, R.Morad, V.Sokhin, IEEE
International Conference on Computer Design (ICCD 2016), October 2016.
“Anatomy of Microarchitecture-Level Reliability
Assessment: Throughput and Accuracy”, A.Chatzidimitriou, D.Gizopoulos,
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS
2016), Uppsala, Sweden, April, 2016.
“GUFI: a Framework for GPUs Reliability Assessment”, S.Tselonis, D.Gizopoulos,
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS
2016), Uppsala, Sweden, April, 2016.
“Microprocessor Reliability-Performance Tradeoffs
Assessment at the Microarchitecture Level”,
S.Tselonis, M.Kaliorakis, N.Foutris, G.Papadimitriou, D.Gizopoulos, IEEE VLSI Test Symposium (VTS 2016), Las Vegas, NV, USA, April, 2016.
“Faults in Data Prefetchers: Performance Degradation
and Variability”, N.Foutris,
A.Chatzidimitriou, D.Gizopoulos,
J.Kalamatianos, V.Sridharan,
IEEE VLSI Test Symposium (VTS 2016),
Las Vegas, NV, USA, April, 2016.
“Differential Fault Injection on Microarchitectural
Simulators”, M.Kaliorakis,
S.Tselonis, A.Chatzidimitriou,
N.Foutris, D.Gizopoulos,
IEEE International Symposium on Workload Characterization (IISWC
2015), Atlanta, GA, USA, October 2015.
“Accelerated Microarchitectural Fault
Injection-Based Reliability Assessment”,
M.Kaliorakis, S.Tselonis, A.Chatzidimitriou, D.Gizopoulos,
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
(DFTS 2015), Amherst, MA, USA, October 2015. [Best paper award nomination] 
“Efficient Parallelization of the Discrete
Wavelet Transform Algorithm using Memory-oblivious Optimizations”, A.Keliris, O.Kremmyda,
V.Dimitsas, M.Maniatakos, D.Gizopoulos, IEEE International Workshop on Power and
Timing Modeling, Optimization and Simulation (PATMOS 2015), Salvador, Bahia,
Brazil, September 2015. [Best paper
award]
“Hierarchical Synthesis of Quantum and Reversible
Architectures”, A.Pavlidis and D.Gizopoulos,
ACM International Conference on Computing Frontiers (CF 2015), Ischia, Italy,
May 2015. [Best paper award nomination] 
“Accelerated Online Error Detection in Many-core
Microprocessor Architectures”, M.Kaliorakis, M.Psarakis, N.Foutris, D.Gizopoulos, IEEE
VLSI Test Symposium (VTS 2014), Napa, CA, USA, April, 2014.
“Assessing the Impact of Hard Faults in Performance
Components of Modern Microprocessors”, N.Foutris, D.Gizopoulos, J.Kalamatianos, V.Sridharan, IEEE
International Conference on Computer Design (ICCD 2013), Asheville, NC, USA,
October 2013.
“Fast Quantum Modular Exponentiation Architecture for
Shor’s Factorization Algorithm”, A.Pavilidis and D.Gizopoulos,
Quantum Information and Computation (QIC) journal, accepted for publication.
“Deconfigurable Microprocessor Architectures for Silicon Debug
Acceleration”, N.Foutris,
D.Gizopoulos, X.Vera, A.Gonzalez, ACM/IEEE International Symposium on Computer
Architecture (ISCA 2013), Tel-Aviv, Israel, June 2013. [HiPEAC paper award] 
“The Functional and Performance Tolerance of GPUs to
Permanent Faults in Registers”, S.Tselonis, V.Dimitsas, D.Gizopoulos, IEEE International On-Line Testing Symposium
(IOLTS 2013),
Chania, Greece, July 2013.
“Reliability Challenges of Real-Time Systems in
Forthcoming Technology Nodes”, S.Hamdioui, D.Gizopoulos, G.Guido, M.Nicolaidis, A.Grasset, P.Bonnot, ACM/IEEE
Design, Automation, and Test in Europe Conference (DATE 2013), Grenoble, France,
April 2013.
“Accelerating Microprocessor Silicon Validation by
Exposing ISA Diversity”, N.Foutris, D.Gizopoulos, M.Psarakis, X.Vera, A.Gonzalez, ACM/IEEE International Symposium on
Microarchitecture (MICRO 2011), Porto Alegre, Brazil, December, 2011. [HiPEAC paper award] 
“Architectures for Online Error Detection and Recovery
in Multicore Processors”, D.Gizopoulos, M.Psarakis, S.V.Adve, P.Ramachandran S.K.S.Hari, D.Sorin, A.Meixner, A.Biswas, X.Vera, ACM/IEEE Design, Automation, and Test in Europe
Conference (DATE 2011), Grenoble, France, April 2011.
“MT-SBST: Self-Test Optimization in Multithreaded
Multicore Architectures”, N.Foutris, M.Psarakis, D.Gizopoulos, X.Vera, A.Gonzalez, IEEE International Test Conference (ITC 2010), Austin, Texas, USA,
November 2010.
“Microprocessors Software-Based Self-Testing”, M.Psarakis, D.Gizopoulos,
E.Sanchez, M.Sonza Reorda,
IEEE Design & Test of Computers Magazine (D&T), vol. 27, no. 3, pp.
4-19, May-June 2010.
“Effective Software-Based Self-Test Strategies for
On-Line Periodic Testing of Embedded Processors”,
A.Paschalis, D.Gizopoulos,
IEEE Design Automation and Test in Europe Conference (DATE 2004), Paris, France,
February 2004. [Best paper award
nomination]
“Low-Cost Software-Based Self-Testing of RISC Processor
Cores”, N.Kranitis, Y.Xenoulis, D.Gizopoulos, A.Paschalis, Y.Zorian, IEEE Design
Automation and Test in Europe Conference (DATE 2003), Munich, Germany,
March 2003. [Best paper award
nomination]
Books
“Dependable
Multicore Architectures at Nanoscale”, M.Ottavi,
D.Gizopoulos, S.Pontarelli
(editors), Springer, July 2017, ISBN-10: 3319544217, ISBN-13: 978-3319544212.
“Advances in
Electronic Testing: Challenges and Methodologies”, D.Gizopoulos
(editor), Springer, January 2006, ISBN 0387294082 (link).
“Embedded
Processor-Based Self-Test”, D.Gizopoulos, A.Paschalis, Y.Zorian, Springer, December
2004, ISBN 1-4020-2785-0 (link).
Patent
“Built-In
Self-Test Method and Apparatus for Booth Multipliers”, D.Gizopoulos, A.Paschalis and Y.Zorian, United States Patent No 5,960,009, September 28,
1999.
Book
Translations
“An
Introduction to Parallel Programming”, P.Pacheco,
Elsevier – Morgan Kaufmann (Greek translation published by Klidarithmos publications 2015).
“Programming
Massively Parallel Processors”, D.Kirk, W.Hwu, Elsevier – Morgan Kaufmann / Nvidia (Greek translation published by Klidarithmos
publications 2011).
“Computer
Organization and Design: The Hardware/Software Interface”, D.A.Patterson, J.L.Hennessy, 4rd
edition, Elsevier – Morgan Kaufmann (Greek translation published by Klidarithmos publications 2010).
“Computer
Organization and Design: The Hardware/Software Interface”, D.A.Patterson, J.L.Hennessy, 3rd
edition, Elsevier – Morgan Kaufmann (Greek translation published by Klidarithmos publications 2006).
“Digital Design:
An Embedded Systems Approach using VHDL”, P.Ashenden,
Elsevier – Morgan Kaufmann, (Greek translation published by New
Technologies publications 2010).
“Modern
Operating Systems”, 3rd edition, A.Tanenbaum,
Pearson Prentice-Hall, (Greek translation published by Klidarithmos
publications 2009).
Research
Support from Industry
AMD
– unrestricted research grant.
Cisco – unrestricted
research grant.
IBM
research – faculty award and shared
university research award.
Nvidia – equipment donation (graphics cards).
Intel – MARC
(Many-core Applications Research Community) – Test Scheduling in
Massively Parallel Architectures: Intel’s SCC – single chip cloud
computer.
AMD – equipment donation (workstations).
Sun/Oracle – equipment
donation (workstation).
Teaching
|
University of Athens Computer Architecture I (undergraduate) (link to eclass) Computer Architecture II (undergraduate) (link to eclass) Advanced Computer Architecture (graduate) (link to eclass) |
University
of Piraeus (past) Computer Architecture
(undergrad) Advanced Computer
Architecture (undergrad) Operating Systems
(undergrad) Computer Systems
Reliability (undergrad) Advanced Logic Design
using VHDL (undergrad) |
Embedded Systems
Modeling (graduate) Real-Time Operating
Systems (graduate) Modern Processors
(graduate) Computer Organization
(graduate) Operating Systems
(graduate) |
Service
General Chair
IEEE
International Symposium on Defect and Fault Tolerance (DFTS), October 2009,
Chicago, IL, USA.
IEEE
International On-Line Testing Symposium (IOLTS), July 2003, Kos, Greece.
IEEE
European Test Workshop (ETW), May 2002, Corfu, Greece.
IEEE Computer Society,
Test Technology Technical Council (TTTC), Tutorials and Education Group, 2005
– 2012.
Program Chair
IEEE International
On-Line Testing Symposium (IOLTS) 2017, 2016, 2015, 2014, 2013, 2012, 2011,
2010, 2009, 2008, 2007.
IEEE Workshop on
Silicon Errors in Logic – System Effects (SELSE) 2015, 2014.
IEEE International
Workshop on Design for Reliability and Variability (DRV), 2011
IEEE
International Symposium on Defect and Fault Tolerance (DFTS) 2008.
IEEE
International Workshop on Infrastructure Intellectual Property (IP), 2006,
2005, 2004, 2003.
IEEE Computer Society
TTTC, Test Technology Educational Program (TTEP), Tutorials Group, 2004, 2003,
2002, 2001, 2000.
Steering/Advisory Committee Member
IEEE International
Test Conference (ITC): 2004 – 2008.
IEEE European Test
Symposium – (ETS): 2001 – 2006 (chairman 2001 – 2003).
IEEE International
Symposium on Quality of Electronic Design (ISQED): 2000 – 2005.
Workshops Chair
IEEE International
Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil
, December 4-8, 2011.
Program Committee Member (including):
IEEE International
Symposium on Workload Characterization (IISWC): 2017
ACM/IEEE International
Conference on Hardware/Software Codesign and System
Synthesis (CODES+ISSS): 2017, 2016.
IEEE International
Conference on Computer Design (ICCD): 2017, 2016.
IEEE International
Test Conference (ITC): 2017, 2016, 2014.
IEEE International
Test Conference Asia (ITC-Asia): 2017.
ACM International
Conference on Computing Frontiers (CF): 2015, 2014.
IEEE VLSI Test
Symposium (VTS): 2017, 2016, 2015, 2014, 2013, 2012, 2011, 2010, 2009, 2008,
2007, 2006, 2005, 2004, 2003, 2002.
IEEE/IFIP
International Conference on Embedded and Ubiquitous Computing (EUC): 2016,
2015, 2014.
IEEE International
Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
(SAMOS), 2016, 2015, 2014, 2013, 2012.
IEEE/ACM Design,
Automation and Test in Europe Conference (DATE): 2016, 2012, 2011, 2010, 2009,
2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.
IEEE European Test
Symposium (ETS): 2017, 2016, 2015,
2014, 2013, 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002,
2001, 2000, 1999.
IEEE International
On-Line Testing Symposium (IOLTS): 2017, 2016, 2015, 2014, 2013, 2012, 2011, 2010,
2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.
IEEE Defect and Fault
Tolerance in VLSI Systems Symposium (DFTS): 2017, 2016, 2015, 2014, 2013, 2012,
2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.
IEEE Asian Test Symposium
(ATS): 2016, 2015, 2014, 2012, 2008.
IEEE Silicon Errors in
Logic – System Effects Workshop (SELSE): 2017, 2016, 2015, 2014.
ACM/IFIP International
Conference on VLSI-SoC (VLSI-SoC):
2010, 2009, 2008.
IEEE International
Workshop on Testing of Embedded Core-based Systems (TECS): 2002, 2001, 2000,
1999, 1998, 1997.
IEEE International
Workshop on Silicon Debug and Diagnosis (SDD): 2007, 2006, 2005.
IEEE International
Symposium on Design of Electronic Systems, Theory and Applications (DELTA): , 2008, 2006, 2004, 2002.
IEEE Latin American
Test Workshop (LATW): 2012, 2011, 2010, 2009, 2008, 2007.
HiPEAC Workshop on Design for Reliability (DFR):
2013, 2012, 2011, 2010.
External Review Committee Member:
IEEE
International Symposium on High-Performance Computing (HPCA), 2015.
IEEE
International Symposium on Computer Architecture (ISCA), 2015.
Also:
Finance
Chair, Publicity Chair, Publications Chair, Tutorials Chair, Audio/Visual
Chair, Sponsors Chair, Regional Liaison
for several conferences.
Society
and Networks Membership
IEEE Fellow (Fellow:
2013, Senior member: 2003; Member: 1997; Student member: 1993).
IEEE
Computer Society Golden Core Member (since 2002).
ACM
Senior Member (2017).
HiPEAC Member.
Last update: May 2017.