Dimitris Gizopoulos

Associate Professor, University of Athens, Department of Informatics & Telecommunications

IEEE Fellow (Class of 2013)

Contact information:

Mailing address:

University of Athens, Department of Informatics and Telecommunications

Panepistimiopolis, Ilissia, GR 157 84, Athens, Greece (Office A32, 1st floor)

Phone: +30 210 727 5145

Fax: +30 210 727 5214

Email: dgizop AT di DOT uoa DOT gr

@Cal.Di.Uoa (follow Computer Architecture Lab on Twitter)

I am Associate Professor at the Department of Informatics & Telecommunications (link) of the National & Kapodistrian University of Athens (link) in Greece (since May 2011) where I am leading the Computer Architecture group of the Digital Systems and Computer Architecture laboratory.

I received my engineering diploma from the Department of Computer Engineering & Informatics of the University of Patras (1992) and my PhD from the Department of Informatics & Telecommunications of the National & Kapodistrian University of Athens (1997). Before joining the University of Athens, I was Lecturer, Assistant Professor, and Associate Professor at the Department of Informatics of the University of Piraeus (1999 – 2011). Before that, I worked as post-doc fellow at the Institute of Informatics and Telecommunications of the NCSR “Demokritos” (1999) and as research engineer in the private sector (1997 – 1999). My research work is in the area of Dependable Computer Architecture, and in particular on-line testing, fault tolerance, and design validation of Microprocessors and Microprocessor-based systems. I have introduced techniques for efficient ISA-based error and bug detection in different microprocessor architectures and test time optimization techniques for multithreaded and multicore architectures. Currently, my research focuses on silicon debug/validation of microprocessor architectures, microprocessors reliability evaluation, error detection and fault tolerance in massively parallel architectures including GPUs, as well as memory system design for massively parallel architectures.

Group research funded by:

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Supported by:

Editorships

Member of Editorial Boards:

IEEE Transactions on VLSI Systems, 2009 – present (link).

IEEE Transactions on Computers, 2007 – 2012 (link).

IEEE Design & Test of Computers, 2002 – present (link).

Springer Journal of Electronic Testing: Theory and Applications, 2006 – present (link).

Special Issues Guest Editor:

IEEE Transactions on Computers (January 2011) topic “Dependable Computer Architecture” (guest editorial).

IEEE Transactions on VLSI Systems (April 2007) topic “Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems” (guest editorial).

IEEE Design & Test of Computers (May-June 2004) topic “Design for Yield and Reliability” (guest editorial).

IEEE Communications Magazine (September 2003) topic “Testing and Verification of Communication System-on-Chip Devices” (guest editorial).

Springer Journal of Electronic Testing: Theory and Applications, topic “Manufacturable and Dependable Multicore Architectures at Nanoscale”.

Funded Research Projects

CLERECO [Cross-Layer Early Reliability Evaluation for the Computing cOntinuum], FP7 STREP (starts October 1, 2013).

HOLISTIC [Hardware and Software Techniques for Multicore Processor Architectures Reliability Enhancement], “Thales” research program, Ministry of Education

DIaSTEMA [Data-Intensive Space Applications on Emerging Massively Parallel Processor Architectures: Performance, Energy, and Dependability Opportunities], “Greek-China Research Collaboration 2012-2015”, Ministry of Education

AMD/UoA – unrestricted research grant.

Cisco/UoA – unrestricted research grant.

Networks of Excellence

MEDIAN [manufacturable and dependable multicore architectures at nanoscale], ESF COST Action, member, Vice-Chair (link)

HiPEAC [European Network of Excellence on High Performance and Embedded Architecture and Compilation], FP7, member (link)

Publications/Citations

DBLP Bibliography Google Scholar Microsoft Academic Research

Recent Highlights

“Assessing the Impact of Hard Faults in Performance Components of Modern Microprocessors”, N.Foutris, D.Gizopoulos, J.Kalamatianos, V.Sridharan, IEEE International Conference on Computer Design (ICCD 2013), Asheville, NC, USA, October 2013.

“Fast Quantum Modular Exponentiation Architecture for Shor’s Factorization Algorithm”, A.Pavilidis and D.Gizopoulos, Quantum Information and Computation (QIC) journal, accepted for publication.

“Deconfigurable Microprocessor Architectures for Silicon Debug Acceleration”, N.Foutris, D.Gizopoulos, X.Vera, A.Gonzalez, ACM/IEEE International Symposium on Computer Architecture (ISCA 2013), Tel-Aviv, Israel, June 2013. [HiPEAC paper award]

“The Functional and Performance Tolerance of GPUs to Permanent Faults in Registers”, S.Tselonis, V.Dimitsas, D.Gizopoulos, IEEE International On-Line Testing Symposium (IOLTS 2013), Chania, Greece, July 2013.

“Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes”, S.Hamdioui, D.Gizopoulos, G.Guido, M.Nicolaidis, A.Grasset, P.Bonnot, ACM/IEEE Design, Automation, and Test in Europe Conference (DATE 2013), Grenoble, France, April 2013.

“Accelerating Microprocessor Silicon Validation by Exposing ISA Diversity”, N.Foutris, D.Gizopoulos, M.Psarakis, X.Vera, A.Gonzalez, ACM/IEEE International Symposium on Microarchitecture (MICRO 2011), Porto Alegre, Brazil, December, 2011. [HiPEAC paper award]

“Architectures for Online Error Detection and Recovery in Multicore Processors”, D.Gizopoulos, M.Psarakis, S.V.Adve, P.Ramachandran S.K.S.Hari, D.Sorin, A.Meixner, A.Biswas, X.Vera, ACM/IEEE Design, Automation, and Test in Europe Conference (DATE 2011), Grenoble, France, April 2011.

“MT-SBST: Self-Test Optimization in Multithreaded Multicore Architectures”, N.Foutris, M.Psarakis, D.Gizopoulos, X.Vera, A.Gonzalez, IEEE International Test Conference (ITC 2010), Austin, Texas, USA, November 2010.

“Microprocessors Software-Based Self-Testing”, M.Psarakis, D.Gizopoulos, E.Sanchez, M.Sonza Reorda, IEEE Design & Test of Computers Magazine (D&T), vol. 27, no. 3, pp. 4-19, May-June 2010.

Selected Journals/Transactions (40 journals/transactions in total)

“Fast Quantum Modular Exponentiation Architecture for Shor’s Factorization Algorithm”, A.Pavilidis and D.Gizopoulos, Quantum Information and Computation (QIC) journal, accepted for publication.

“Efficient Memory Repair using Cache-based Redundancy”, N.Axelos, K.Pekmestzi, D.Gizopoulos, IEEE Transactions on VLSI Systems, vol. 20, no. 12, pp. 2278-2288, December 2012.

“Microprocessors Software-Based Self-Testing”, M.Psarakis, D.Gizopoulos, E.Sanchez, M.Sonza Reorda, IEEE Design & Test of Computers Magazine, vol. 27, no. 3, pp. 4-19, May-June 2010.

“A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches”, G.Theodorou, N.Kranitis, A.Paschalis, D.Gizopoulos, IEEE Transactions on VLSI Systems, accepted for publication.

“Chip Self-Organization and Fault-Tolerance in Massively Defective Multicore Arrays”, J.Collet, P.Zajac, M.Psarakis, D.Gizopoulos, IEEE Transactions on Dependable and Secure Computing, vol. 8, no. 2, pp. 207-217, March-April 2011.

“Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors”, A.Apostolakis, D.Gizopoulos, M.Psarakis, A.Paschalis, IEEE Transactions on Computers, vol. 58, no. 12, pp. 1682-1694, December 2009.

“Low Energy On-Line Self-Test of Embedded Processors in Dependable WSN Nodes”, A.Merentitis, N.Kranitis, A.Paschalis, D.Gizopoulos, IEEE Transactions on Dependable and Secure Computing, vol. 9, no. 1, pp. 86-100, January-February 2012.

“Accumulator based 3-Weight Pattern Generation”, A.Paschalis, I.Voyiatzis, D.Gizopoulos, IEEE Transactions on VLSI Systems, vol. 20, no. 2, pp. 357-361, February 2012.

“Online Periodic Self-Test Scheduling for Real-Time Processor-Based Systems Dependability Enhancement”, D.Gizopoulos, IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 2, pp. 152-158, April-June 2009.

“Instruction-based On-line Periodic Self-testing of Microprocessors With Floating-point Units”, G.Xenoulis, D.Gizopoulos, M.Psarakis, A.Paschalis, IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 2, pp. 124-134, April-June 2009.

“Test Program Generation for Communication Peripherals in Processor-Based Systems-on-Chip”, A.Apostolakis, D.Gizopoulos, M.Psarakis, D.Ravotto, M.Sonza Reorda, IEEE Design & Test of Computers Magazine, vol. 26, no. 2, pp. 52-63, March-April 2009.

“Systematic Software-Based Self-Test for Pipelined Processors”, D.Gizopoulos, M.Psarakis, M.Hatzimihail, M.Maniatakos, A.Paschalis, A.Raghunathan, S.Ravi, IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 11, pp. 1441-1453, November 2008.

“Recursive Pseudo-Exhaustive Two-pattern Generation”, I.Voyiatzis, D.Gizopoulos, A.Paschalis, IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 1, pp. 142-152, January 2010.

“An Input Vector Monitoring Concurrent BIST Architecture Based on a Pre-computed Test Set”, I.Voyiatzis, A.Paschalis, D.Gizopoulos, C.Halatsis, E.Marki, M.Hatzimihail, IEEE Transactions on Computers, vol. 57, no. 8, pp. 1012-1022, August 2008.

“Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip”, A.Apostolakis, M.Psarakis, D.Gizopoulos, A.Paschalis, IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 8, pp. 971-975, August 2007.

“Hybrid Software-Based Self-Test (H-SBST): Methodology and Application on a Modern Processor Core”, N.Kranitis, A.Merentitis, G.Theodorou, A.Paschalis, D.Gizopoulos, IEEE Design and Test of Computers, vol. 25, no. 1, pp. 64-75, January-February 2008.

“Testability Analysis and Scalable Test Generation for High-Speed Floating Point Units", G.Xenoulis, D.Gizopoulos, M.Psarakis and A.Paschalis, IEEE Transactions on Computers, vol. 55, no. 11, pp. 1449-1457, November 2006.

“Accumulator-based Test Generation for Robust Sequential Fault Testing in DSP cores in Near-optimal Time”, I.Voyiatzis, D.Gizopoulos, A.Paschalis, IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 9, pp. 1079-1086, September 2005.

“Software-Based Self-Testing of Embedded Processors”, N.Kranitis, G.Xenoulis, A.Paschalis, D.Gizopoulos, IEEE Transactions on Computers, vol. 54, no. 4, pp. 461-475, April 2005.

“Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors”, A.Paschalis, D.Gizopoulos, IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 24, no. 1, pp. 88-99, January 2005.

“Built-In Sequential Fault Self-Testing of Array Multipliers”, M.Psarakis, D.Gizopoulos, A.Paschalis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 449-460, March 2005.

“A Concurrent Built-In Self-Test Architecture Based on a Self-Testing RAM”, I.Voyiatzis, A.Paschalis, D.Gizopoulos, N.Kranitis, C.Halatsis, IEEE Transactions on Reliability, vol. 54, no. 1, pp. 69-78, March 2005.

“Low-cost, on-line self-testing of processor cores based on embedded software routines”, D.Gizopoulos, Elsevier, Microelectronics Journal, vol. 35, no. 5, pp. 443-449, 2004

“Easily Testable Cellular Carry Lookahead Adders”, D.Gizopoulos, M.Psarakis, A.Paschalis, Y.Zorian, Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers/IEEE Computer Society, vol. 19, no 3, pp. 285-298, June 2003.

“Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays”, M.Psarakis, D.Gizopoulos, A.Paschalis, and Y.Zorian, IEEE Transactions on Computers, vol. 49, no. 10, pp. 1083-1099, October 2000.

“Power/Energy Efficient Built-In Self-Test Schemes for Processor Datapaths”, N.Kranitis, D.Gizopoulos, A.Paschalis, M.Psarakis and Y.Zorian, IEEE Design & Test of Computers, vol. 17, no. 4, pp. 15-28, October-December 2000. Special Issue on Microprocessor Test and Verification.

“An Effective Built-In Self-Test Scheme for Array Multipliers”, D.Gizopoulos, A.Paschalis and Y.Zorian, IEEE Transactions on Computers, vol. 48, no. 9, pp. 936-950, September 1999.

“Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools”, M.Psarakis, D.Gizopoulos and A.Paschalis, Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers/IEEE Computer Society, vol. 13, no. 3, pp.315-319, December 1998.

“An Effective Built-In Self-Test Scheme for Booth Multipliers”, D.Gizopoulos, A.Paschalis and Y.Zorian, IEEE Design & Test of Computers, vol. 15, no. 3, pp. 105-111, July-September 1998.

“C-Testable Modified Booth Multipliers”, D.Gizopoulos, D.Nikolos, A.Paschalis and C.Halatsis, Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers/IEEE Computer Society, vol. 8, no. 3, pp. 241-259, June 1996.

Selected Conferences (75 conferences in total)

“Combining Checkpointing and Scrubbing in FPGA-based Real-Time Systems”, A.Sari, M.Psarakis, D.Gizopoulos, IEEE VLSI Test Symposium (VTS 2013), Berkeley, CA, USA, May, 2013.

“A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches”, G.Theodorou, N.Kranitis, A.Paschalis, D.Gizopoulos, IEEE International Test Conference (ITC 2011), Anaheim, California, USA, September 2011.

“Towards Improved Survivability in Safety-Critical Systems”, J.Abella, F.J.Cazorla, E.Quinones, D.Gizopoulos, A.Grasset, S.Yehia, P.Bonnot, R.Mariani, G.Bernat, IEEE International On-Line Testing Symposium (IOLTS 2011), Athens, Greece, July 2011.

“Energy-Optimal On-Line Self-Test of Microprocessors in WSN Nodes”, A.Merentitis, A.Paschalis, D.Gizopoulos, N.Kranitis, IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, The Netherlands, October 2010.

“SBST for On-Line Detection of Hard Faults in Multiprocessor Applications Under Energy Constraints”, A.Merentitis, D.Margaris, N.Kranitis, A.Paschalis, D.Gizopoulos, IEEE International On-Line Testing Symposium (IOLTS 2010), Corfu, Greece, July 2010.

“Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors”, A.Apostolakis, M.Psarakis, D.Gizopoulos, A.Paschalis, I.Parulkar, IEEE European Test Symposium (ETS 2009), Sevilla, Spain, May 2009.

“Enhanced Self-Configurability and Yield in Multicore Grids”, E.Kolonis, M.Nicolaidis, D.Gizopoulos, M.Psarakis, J.Collet, P.Zajac, in Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), Sesimbra, Portugal, pp. 75-80, June 2009.

“Low Energy On-Line SBST of Embedded Processors”, A.Merentitis, N.Kranitis, A.Paschalis, D.Gizopoulos, in Proceedings of the IEEE International Test Conference (ITC 2008), Santa Clara, California, USA, October 2008.

“Functional Self-Testing for Bus-Based Symmetric Multiprocessors”, A.Apostolakis, M.Psarakis, D.Gizopoulos, A.Paschalis, in Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE 2008), Munich, Germany, pp. 1304-1309, March 2008.

“A Methodology for Detecting Performance Faults in Microprocessor Speculative Execution Units via Hardware Performance Monitoring”, M.Hatzimihail, M.Psarakis, D.Gizopoulos, A.Paschalis, IEEE International Test Conference (ITC 2007), Santa Clara, California, USA, October 2007.

“On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors”, G.Xenoulis, M.Psarakis, D.Gizopoulos, A.Paschalis, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 2007), Rome, Italy, pp. 379-397, September 2007.

“Selecting Power-Optimal SBST Routines for On-Line Processor Testing”, A.J.Merentitis, N.Kranitis, A.Paschalis, D.Gizopoulos, IEEE European Test Symposium (ETS 2007), Freiburg, Germany, May 2007.

“Systematic Software-Based Self-Test for Pipelined Processors”, M.Psarakis, D.Gizopoulos, M.Hatzimihail, A.Paschalis, A.Raghunathan, S.Ravi, ACM/IEEE Design Automation Conference (DAC 2006), San Fransisco, CA, USA, pp. 393-398, July 2006.

“A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs”, P. Kenterlis, N. Kranitis, A. Paschalis, D.Gizopoulos, M.Psarakis, IEEE International On-Line Testing Symposium 2006 (IOLTS 2006), Como, Italy, pp. 235-241, July 2006.

“Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications”, N.Kranitis, A.Merentitis, N.Laoutaris, G.Theodorou, A.Paschalis, D.Gizopoulos, C.Halatsis, in Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE 2006), Munich, Germany, March 2006.

“A Concurrent BIST scheme for online/offline testing based on a precomputed test set”, I.Voyiatzis, D.Gizopoulos, A.Paschalis, C.Halatsis, in Proceedings of the IEEE International Test Conference (ITC 2005), Austin, TX, USA, November, 2005.

“Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors”, A.Paschalis, D.Gizopoulos, IEEE Design Automation and Test in Europe Conference (DATE 2004), Paris, France, February 2004. [Best paper award nomination]

“Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores”, N.Kranitis, G.Xenoulis, A.Paschalis, D.Gizopoulos, Y. Zorian, in Proceedings of the IEEE International Test Conference (ITC 2003), Charlotte, NC, USA, September 30 – October 2, 2003.

“Low-Cost Software-Based Self-Testing of RISC Processor Cores”, N.Kranitis, Y.Xenoulis, D.Gizopoulos, A.Paschalis, Y.Zorian, IEEE Design Automation and Test in Europe Conference (DATE 2003), Munich, Germany, March 2003. [Best paper award nomination]

“Instruction-Based Self-Testing of Processor Cores”, N.Kranitis, D.Gizopoulos, A.Paschalis, Y.Zorian, IEEE VLSI Test Symposium 2002 (VTS 2002), Monterey, CA, USA, pp. 223-228, April 28-May 1, 2002.

“Effective Software Self -Test Methodology for Processor Cores”, N.Kranitis, A.Paschalis, D.Gizopoulos, Y.Zorian, IEEE Design Automation and Test in Europe Conference (DATE 2002), Paris, France, pp. 592-597, March 2002.

“Robust and Low-cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers”, M.Psarakis, D.Gizopoulos, A.Paschalis, N.Kranitis, IEEE VLSI Test Symposium 2001 (VTS 2001), Los Angeles, CA, USA, April 30-May 3, 2001.

“Deterministic Software-Based Self-Testing of Embedded Processor Cores”, A.Paschalis, D.Gizopoulos, N.Kranitis, M.Psarakis, and Y.Zorian, IEEE Design Automation and Test in Europe Conference (DATE 2001), Munich, Germany, March 2001.

“Low Power/Energy BIST Scheme for Datapaths”, D. Gizopoulos, N. Kranitis, A. Paschalis, M. Psarakis, and Y.Zorian, IEEE VLSI Test Symposium 2000 (VTS 2000), Montreal, Canada, April 2000.

“An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers”, M.Psarakis, A.Paschalis, D.Gizopoulos, and Y.Zorian, IEEE VLSI Test Symposium (VTS 1999), Dana Point, CA, USA, pp. 252-258, April 1999.

“An Effective BIST Architecture for Fast Multiplier Cores”, A.Paschalis, M.Psarakis, D.Gizopoulos, N.Kranitis and Y.Zorian, IEEE Design Automation & Test in Europe Conference (DATE 1999), Munich, Germany, pp. 117-121, March 1999

“Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model”, M.Psarakis, A.Paschalis and D.Gizopoulos, in Proc. of the 16th IEEE VLSI Test Symposium (VTS 1998), Monterey, CA, USA, April 1998.

“An Effective BIST Scheme for Arithmetic Logic Units”, D.Gizopoulos, A.Paschalis, Y.Zorian and M.Psarakis, in Proc. of the IEEE International Test Conference 1997 (ITC 1997), pp. 868-877, Washington DC, USA, November 1997.

“Robust Sequential Fault Testing of Iterative Logic Arrays”, D.Gizopoulos, M.Psarakis and A.Paschalis, in Proc. of the 15th IEEE VLSI Test Symposium (VTS 1997), Monterey, CA, USA, pp. 238-244, April 1997.

“An Effective BIST Scheme for Datapaths”, D.Gizopoulos, A.Paschalis and Y.Zorian, in Proc. of the IEEE International Test Conference 1996 (ITC 1996), pp. 76-85, Washington DC, USA, October 1996.

“An Asynchronous Totally Self-Checking Two-Rail Code Error Indicator”, N.Gaitanis, D.Gizopoulos, A.Paschalis and P.Kostarakis, in Proc. of the 14th IEEE VLSI Test Symposium (VTS 1996), Princeton, NJ, USA, pp. 151-156, May 1996.

“An Efficient BIST Scheme for Carry-Save and Carry-Propagate Array Multipliers”, D.Gizopoulos, A.Paschalis and Y.Zorian, in Proc. of the 4th IEEE Asian Test Symposium (ATS 1995), Bangalore, India, pp. 286-292, November 1995.

“An Effective BIST Scheme for Booth Multipliers”, D.Gizopoulos, A.Paschalis and Y.Zorian, in Proc. of the IEEE International Test Conference 1995 (ITC 1995), pp. 824-833, Washington DC, USA, October 1995.

“Testing Combinational Iterative Logic Arrays for Realistic Faults”, D.Gizopoulos, D.Nikolos and A.Paschalis, in Proc. of the 13th IEEE VLSI Test Symposium (VTS 1995), Princeton, NJ, USA, pp. 35-40, May 1995.

“C-Testable Multipliers based on the Modified Booth Algorithm”, D.Gizopoulos, D.Nikolos, A.Paschalis and P.Kostarakis, in Proc. of the 3rd IEEE Asian Test Symposium (ATS 1994), Nara, Japan, pp. 163-168, November 1994.

Books

“Advances in Electronic Testing: Challenges and Methodologies”, D.Gizopoulos (editor), Springer, January 2006, ISBN 0387294082 (link).

“Embedded Processor-Based Self-Test”, D.Gizopoulos, A.Paschalis, Y.Zorian, Springer, December 2004, ISBN 1-4020-2785-0 (link).

Patent

“Built-In Self-Test Method and Apparatus for Booth Multipliers”, D.Gizopoulos, A.Paschalis and Y.Zorian, United States Patent No 5,960,009, September 28, 1999.

Book Translations

“Programming Massively Parallel Processors”, D.Kirk, W.Hwu, Elsevier – Morgan Kaufmann / Nvidia (Greek translation published by Klidarithmos publications 2011).

“Computer Organization and Design: The Hardware/Software Interface”, D.A.Patterson, J.L.Hennessy, 4rd edition, Elsevier – Morgan Kaufmann (Greek translation published by Klidarithmos publications 2010).

“Computer Organization and Design: The Hardware/Software Interface”, D.A.Patterson, J.L.Hennessy, 3rd edition, Elsevier – Morgan Kaufmann (Greek translation published by Klidarithmos publications 2006).

“Digital Design: An Embedded Systems Approach using VHDL”, P.Ashenden, Elsevier – Morgan Kaufmann, (Greek translation published by New Technologies publications 2010).

“Modern Operating Systems”, 3rd edition, A.Tanenbaum, Pearson Prentice-Hall, (Greek translation published by Klidarithmos publications 2009).

Research Support from Industry

AMD – unrestricted research grant.

Cisco – unrestricted research grant.

Nvidia – equipment donation (graphics cards).

Intel – MARC (Many-core Applications Research Community) – Test Scheduling in Massively Parallel Architectures: Intel’s SCC – single chip cloud computer.

AMD – equipment donation (workstations).

Sun/Oracle – equipment donation (workstation).

Teaching

University of Athens

Computer Architecture I (undergraduate) (link to eclass)

Computer Architecture II (undergraduate) (link to eclass)

Advanced Computer Architecture (graduate) (link to eclass)

University of Piraeus (past)

Computer Architecture (undergrad)

Advanced Computer Architecture (undergrad)

Operating Systems (undergrad)

Computer Systems Reliability (undergrad)

Advanced Logic Design using VHDL (undergrad)

Embedded Systems Modeling (graduate)

Real-Time Operating Systems (graduate)

Modern Processors (graduate)

Computer Organization (graduate)

Operating Systems (graduate)

Organizing and Steering Committees

General Chair

IEEE International Symposium on Defect and Fault Tolerance (DFTS), October 2009, Chicago, IL, USA.

IEEE International On-Line Testing Symposium (IOLTS), July 2003, Kos, Greece.

IEEE European Test Workshop (ETW), May 2002, Corfu, Greece.

IEEE Computer Society, Test Technology Technical Council (TTTC), Tutorials and Education Group, 2005 – 2012.

Vice General Chair

IEEE International On-Line Testing Symposium (IOLTS), July 2005, San Rafael, France.

IEEE International On-Line Testing Symposium (IOLTS), July 2004, Madeira, Portugal.

IEEE European Test Workshop (ETW), May 2001, Stockholm, Sweden.

Program Chair

IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE) 2014.

IEEE International On-Line Testing Symposium (IOLTS) 2013, 2012, 2011, 2010, 2009, 2008, 2007.

IEEE International Workshop on Design for Reliability and Variability (DRV), 2011

IEEE International Symposium on Defect and Fault Tolerance (DFTS) 2008.

IEEE International Workshop on Infrastructure Intellectual Property (IP), 2006, 2005, 2004, 2003.

IEEE Computer Society TTTC, Test Technology Educational Program (TTEP), Tutorials Group, 2004, 2003, 2002, 2001, 2000.

Steering/Advisory Committee Member

IEEE International Test Conference (ITC): 2004 – 2008.

IEEE European Test Symposium – (ETS): 2001 – 2006 (chairman 2001 – 2003).

IEEE International Symposium on Quality of Electronic Design (ISQED): 2000 – 2005.

Workshops Chair

IEEE International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil , December 4-8, 2011.

Tutorials Chair

IEEE Latin American Test Workshop (LATW), 2012, 2011, 2008, 2007, 2006.

Finance Chair, Publicity Chair, Publications Chair, Audio/Visual Chair, Sponsors Chair, Regional Liason for several conferences.

Program Committees

Topic Chair-Coordinator / Special Sessions-Tracks Organizer

Topic Chair for “On-Line Test and Fault Tolerance”, IEEE Design Automation and Test in Europe Conference (DATE 2011, 2010, 2009).

Co-Organizer for Special Technical Day on Intellectual Property (IP), IEEE Design Automation and Test in Europe Conference (DATE 2002).

Topic Co-chair for ‘Test Resource Partitioning and System Test”, IEEE Design Automation and Test in Europe Conference (DATE 2003, 2002).

Topic Co-chair for “Testing Embedded Cores and Systems”, IEEE Design Automation and Test in Europe Conference (DATE 2001).

Innovative Practices Track Chair, IEEE VLSI Test Symposium (VTS 2004, 2003).

Topic Coordinator for “On-Line and Off-Line BIST Techniques”, IEEE International On-Line Testing Workshop (IOLTS 2002, 2001, 2000).

Program Committee Member

IEEE VLSI Test Symposium (VTS): 2013, 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002.

IEEE/ACM Design, Automation and Test in Europe Conference (DATE): 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.

IEEE European Test Symposium (ETS): 2013, 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000, 1999.

IEEE International On-Line Testing Symposium (IOLTS): 2013, 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.

IEEE Defect and Fault Tolerance in VLSI Systems Symposium (DFTS): 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.

IEEE Asian Test Symposium (ATS): 2012, 2008.

ACM/IFIP International Conference on VLSI-SoC (VLSI-SoC): 2010, 2009, 2008.

IEEE International Workshop on Testing of Embedded Core-based Systems (TECS): 2002, 2001, 2000, 1999, 1998, 1997.

IEEE International Workshop on Silicon Debug and Diagnosis (SDD): 2007, 2006, 2005.

IEEE International Symposium on Design of Electronic Systems, Theory and Applications (DELTA): , 2008, 2006, 2004, 2002.

IEEE Latin American Test Workshop (LATW): 2012, 2011, 2010, 2009, 2008, 2007.

HiPEAC Workshop on Design for Reliability (DFR): 2013, 2012, 2011, 2010.

Society and Networks Membership

IEEE Fellow (Fellow: 2013, Senior member: 2003; Member: 1997; Student member: 1993).

IEEE Computer Society Golden Core Member (since 2002).

ACM Member.

HiPEAC Regular Member.

Last update: September 2013.