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Dimitris Gizopoulos Professor,
University of Athens, Department of
Informatics & Telecommunications
IEEE Fellow (Class of 2013)
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Contact
information: Mailing address: University of Athens, Department of
Informatics and Telecommunications
Panepistimiopolis, Ilissia, GR 157 84,
Athens, Greece (Office A36, 1st floor) Phone: +30 210 727 5145 Fax: +30 210 727 5214 Email: d g I z o p
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I am Professor at the Department of
Informatics & Telecommunications (link)
of the National
& Kapodistrian University of Athens (link)
in Greece where I am leading the Computer
Architecture Laboratory. My group’s research focuses on the area of Dependable and
Energy-Efficient Computer Architecture, and in particular
fault/error tolerance, design correctness validation and their relation to
performance and energy-efficiency for microprocessors and
microprocessor-based systems. I have introduced techniques for efficient
ISA-based error and bug detection in different microprocessor architectures
and test time optimization techniques for multithreaded and multicore
architectures. Currently, our research focuses on computing systems
reliability assessment at the microarchitecture level (for CPUs, GPUs and
other accelerators), the investigation of the voltage and frequency limits of
modern CPUs hardware for energy efficiency and performance boosting, and the
silicon debug/validation of complex microprocessor architectures. Check the Computer Architecture Lab web page:
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Group research
funded/supported by:
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News 
New
Editorial Service – Associate Editor for
IEEE Transactions on Emerging Topics in Computing (TETC), January 2019 –
present (link).
New
Special Issue – Guest Editor for IEEE
Transactions on Device and Materials Reliability (TDMR) Special Issue
“Robust System Design”.
New
Editorial Service – Associate Editor for
IEEE Transactions on Computers (TC), June 2018 – present (link).
New
Special Issue – Guest Editor for IEEE
Transactions on Sustainable Computing Special Issue “Beyond the Energy
& Performance Scaling Boundaries of Modern Computer Architectures” ,
Call for Papers (link).
New
Editorial Service – Associate Editor for
IEEE Transactions on Sustainable Computing (T-SUSC), January 2017 –
present (link).
New Book - “Dependable
Multicore Architectures at Nanoscale”, M.Ottavi,
D.Gizopoulos, S.Pontarelli
(editors), Springer, July 2017 (link to Springer).
Keynote
Talk – “Microarchitecture Level Reliability
Assessment”, China Test Conference 2016, Nantong, China,
July 2016.
IBM
Faculty Award 2016 –Validation of
Cloud Computing Enabling Features: the Address Translation Mechanisms of a High-Performance
Microprocessor.
New
H2020 Project Starts (February 2016) – UniServer: Universal
Micro-Server Ecosystem by Exceeding the Energy and Performance Scaling
Boundaries (link to
project)
Funded Research Projects
UniServer [Universal
Micro-Server Ecosystem by Exceeding the Energy and Performance Scaling
Boundaries], H2020 (February 1, 2016 – July 31, 2019). 
CLERECO [Cross-Layer
Early Reliability Evaluation for the Computing cOntinuum], FP7 STREP (October
1, 2013 – November 30, 2016). – completed
HOLISTIC [Hardware and
Software Techniques for Multicore Processor Architectures Reliability
Enhancement], “Thales” research program, Ministry of
Education – completed
DIaSTEMA [Data-Intensive
Space Applications on Emerging Massively Parallel Processor Architectures:
Performance, Energy, and Dependability Opportunities], “Greek-China
Research Collaboration 2012-2015”, Ministry of Education – completed
AMD/UoA – unrestricted
research grant on “Hardware Faults in Performance Structures
of Microprocessors: Implications Analysis and Hybrid Online Detection and
Diagnosis Methods”.
Cisco/UoA – unrestricted
research grant on “Accelerated Online Detection of Functional
and Performance Errors in Complex Multiprocessor Chips”.
ABB/UoA – Smart
Diagnosis for Reliable and Safety Critical Microprocessor-Based systems
IBM
Research (IBM
Faculty Award 2016) –Validation of
Cloud Computing Enabling Features: the Address Translation Mechanisms of a
High-Performance Microprocessor
Networks
of Excellence
MEDIAN [manufacturable
and dependable multicore architectures
at nanoscale], ESF COST Action, member, Vice-Chair (link) – completed
HiPEAC [European Network of
Excellence on High Performance and Embedded Architecture and Compilation], FP7,
member (link)
Editorial Service
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Member of
Editorial Boards: IEEE Transactions on Emerging Topics in Computing,
2019 – present (link). IEEE Transactions on Computers, 2018 – present
(link). IEEE Transactions on Sustainable Computing, 2017
– present (link). Springer Journal of Electronic Testing: Theory and
Applications, 2006 – present (link). IEEE Transactions on VLSI Systems, 2009 – 2015
(link). IEEE Transactions on Computers, 2007 – 2013 (link). IEEE Design & Test of Computers, 2002 –
2015 (link). |
Special
Issues Guest Editor: IEEE Transactions on Device and Materials
Reliability (March 2019) topic “On-Line Testing and Robust
System Design” IEEE Transactions on Sustainable Computing (early
2019) topic “Beyond the Energy & Performance
Scaling Boundaries of Modern Computer Architectures” (CFP link) IEEE Transactions on Device and Materials
Reliability (March 2017) topic “On-Line Testing and Robust
System Design” (guest
editorial) IEEE Transactions on Computers (January 2011) topic
“Dependable Computer Architecture” (guest
editorial). IEEE Transactions on VLSI Systems (April
2007) topic “Autonomous Silicon Validation and
Testing of Microprocessors and Microprocessor-Based Systems” (guest
editorial). IEEE Design & Test of Computers (May-June 2004)
topic “Design for Yield and Reliability” (guest
editorial). IEEE Communications Magazine (September 2003) topic
“Testing and Verification of
Communication System-on-Chip Devices” (guest
editorial). Springer Journal of Electronic Testing: Theory and
Applications, topic “Manufacturable and
Dependable Multicore Architectures at Nanoscale”. |
Publications/Citations
Full lists: DBLP Bibliography Google Scholar
Microsoft Academic Research
Some Recent Publications (last few
years)
DSN 2019, “Demystifying Soft Error Assessment Strategies
on ARM CPUs: Microarchitectural Fault Injection vs. Neutron Beam
Experiments”, A.Chatzidimitriou, P.Bodmann, G.Papadimitriou, D.Gizopoulos, P.Rech, IEEE/IFIP
International Conference on Dependable Systems and Networks (DSN 2019),
Portland, Oregon, USA, June 2019. [best paper award candidate]
ISPASS 2019 “Assessing the Effects of Low Voltage in Branch
Prediction Units”, A. Chatzidimitriou, G.Papadimitriou,
D.Gizopoulos, S.Ganapathy, J.Kalamatianos, IEEE International Symposium on Performance
Analysis of Systems and Software (ISPASS 2019), Madison, WI, USA, March 2019.
HPCA 2019 “Adaptive Voltage/Frequency Scaling and Core
Allocation for Balanced Energy and Performance on Multicore CPUs”, G.Papadimitriou, A. Chatzidimitriou, D.Gizopoulos,
IEEE International Symposium on High-Performance Computer Architecture (HPCA
2019), Washington, DC, USA, February 2019.
ICCD
2018 – “Analysis
and Characterization of Ultra Low Power Branch Predictors”, A.Chatzidimitriou, G.Papadimitriou,
D.Gizopoulos, S.Ganapathy, J.Kalamatianos, IEEE International Conference on Computer
Design (ICCD 2018), Orlando, FL, USA, October 2018,
IOLTS 2018 –
“HealthLog
Monitor: A Flexible System-Monitoring Linux Service”, A.Chatzidimitriou,
G.Papadimitriou, D.Gizopoulos,
IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS
2018), Platja d’Aro,
Spain, July 2018,
DSN 2018 –
“Measuring and Exploiting
Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs”, K.Tovletoglou, L.Mukhanov, G.Karakonstantis, A.Chatzidimitriou,
G.Papadimitriou, M.Kaliorakis,
D.Gizopoulos, Z.Hadjilambrou,
Y.Sazeides, A.Lampropoulos,
S.Das, P.Vo, IEEE/IFIP
International Conference on Dependable Systems and Networks (DSN 2018),
Luxembourg City, Luxembourg, June 2018.
ISPASS
2018 – “Micro-Viruses
for Fast System-Level Voltage Margins Characterization in Multicore
CPUs”, G.Papadimitriou, A.Chatzidimitriou,
M.Kaliorakis, Y.Vastakis, D.Gizopoulos, IEEE International Symposium on Performance
Analysis of Systems and Software (ISPASS 2018), Belfast, UK, April, 2018.
VTS 2018
– “Multi-faceted
Microarchitecture Level Reliability Characterization for NVIDIA and AMD
GPUs”, A.Vallero, S.Tselonis,
D.Gizopoulos, S.Di Carlo,
IEEE VLSI Test Symposium (VTS 2018), San Francisco, CA, USA, April, 2018.
DATE
2018 – “An
Energy-Efficient and Error-Resilient Server Ecosystem Exceeding Conservative
Scaling Limits”, G.Karakonstantis, K.Tovletoglou, L.Mukhanov, H.Vandierendonck, D.S.Nikolopoulos,
P.Lawthers, P.Koutsovasilis,
M.Maroudas, C.D.Antonopoulos,
C.Kalogirou, N.Bellas, S.Lalis, S.Venugopal, A.Prat-Perez, A.Lampropulos, M.Kleanthous, A.Diavastos, Z.Hadjilambrou, P.Nikolaou, Y.Sazeides, P.Trancoso, G.Papadimitriou, M.Kaliorakis, A.Chatzidimitriou, D.Gizopoulos, S.Das, ACM/IEEE Design, Automation, and Test in Europe Conference
(DATE 2018), Dresden, Germany, March 2018.
CAL
2018 – "Statistical Analysis
of Multicore CPUs Operation in Scaled Voltage Conditions", M.Kaliorakis, A.Chatzidimitriou, G.Papadimitriou, D.Gizopoulos,
IEEE Computer Architecture Letters, vol. 17, no. 2, pp. 109-112, July-December
2018.
MICRO
2017 – “Harnessing Voltage Margins for Energy
Efficiency in Multicore CPUs”, G.Papadimitriou,
M.Kaliorakis, A.Chatzidimitriou,
D.Gizopoulos, P.Lawthers, S.Das, IEEE/ACM International Symposium on
Microarchitecture (MICRO 2017), Boston, MA, USA, October 2017.
ISCA 2017
– “MeRLiN: Exploiting Dynamic Instruction
Behavior for Fast and Accurate Microarchitecture Level Reliability
Assessment”, M.Kaliorakis, D.Gizopoulos,
R.Canal, A.Gonzalez,
ACM/IEEE International Symposium on Computer Architecture (ISCA
2017), Toronto, Canada, June 2017
DSN 2017 “RT Level vs. Microarchitecture Level Reliability Assessment:
Case Study on ARM Cortex-A9 CPU”, A.Chatzidimitriou,
M.Kaliorakis, D.Gizopoulos,
M.Iacaruso, M.Pipponzi, R.Mariani, S.Di Carlo, IEEE/IFIP
International Conference on Dependable Systems and Networks (DSN 2017), Denver,
CO, USA, June 2017.
ISPASS 2017 (poster)
– “Multi-faceted Microarchitecture Level Reliability Assessment of
Modern GPU Designs”, A.Vallero, S.Tselonis, S.Di Carlo, D.Gizopoulos, IEEE International Symposium on Performance
Analysis of Systems and Software (ISPASS),
2017 (poster).
VTS 2017 – “Performance-Aware Reliability Assessment of
Heterogeneous Chips”, A.Chatzidimitriou, M.Kaliorakis, S.Tselonis, D.Gizopoulos, IEEE VLSI Test Symposium (VTS 2017), Las Vegas, NV, USA, April, 2017.
IEEE
TDMR 2017 – “An Agile Post-Silicon
Validation Methodology for the Address Translation Mechanisms of Modern
Microprocessors", G.Papadimitriou, A.Chatzidimitriou, D.Gizopoulos, R.Morad, IEEE Transactions on Device and Materials
Reliability (IEEE TDMR), accepted for publication.
IJPP 2016 – “Hierarchical Synthesis of Quantum and Reversible
Architectures", A.Pavlidis, D,Gizopoulos,
Springer, International Journal of Parallel Programming (IJPP), vol. 44, no. 5, pp. 1028-1053, October 2016.
“Cross-Layer
System Reliability Assessment Against Hardware Faults”, A.Vallero, A.Savino, G.Politano, S.Di Carlo, A.Chatzidimitriou, S.Tselonis, M.Kaliorakis, D.Gizopoulos, M.Riera, R.Canal, A.Gonzalez, M.Kooli, A.Bosio, G.Di Natale, IEEE
International Test Conference (ITC 2016), November 2016.
ICCD 2016 –“Unveiling Difficult Bugs in Address Translation Caching Arrays
for Effective Post-Silicon Validation”, G.Papadimitriou,
D.Gizopoulos, A.Chatzidimitriou,
T.Kolan, A.Koyfman, R.Morad, V.Sokhin, IEEE
International Conference on Computer Design (ICCD 2016), October 2016.
ISPASS 2016 – “Anatomy
of Microarchitecture-Level Reliability Assessment: Throughput and Accuracy”, A.Chatzidimitriou, D.Gizopoulos, IEEE International Symposium on Performance
Analysis of Systems and Software (ISPASS 2016),
Uppsala, Sweden, April, 2016.
ISPASS 2016 – “GUFI: a
Framework for GPUs Reliability Assessment”,
S.Tselonis, D.Gizopoulos,
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS
2016), Uppsala, Sweden, April, 2016.
VTS 2016 – “Microprocessor Reliability-Performance
Tradeoffs Assessment at the Microarchitecture Level”,
S.Tselonis, M.Kaliorakis, N.Foutris, G.Papadimitriou, D.Gizopoulos, IEEE VLSI Test Symposium (VTS 2016), Las Vegas, NV, USA, April, 2016.
VTS 2016 – “Faults in Data Prefetchers:
Performance Degradation and Variability”,
N.Foutris, A.Chatzidimitriou,
D.Gizopoulos, J.Kalamatianos,
V.Sridharan, IEEE VLSI Test Symposium (VTS 2016), Las Vegas, NV, USA, April, 2016.
Books
“Dependable
Multicore Architectures at Nanoscale”, M.Ottavi,
D.Gizopoulos, S.Pontarelli (editors),
Springer, July 2017, ISBN-10: 3319544217, ISBN-13: 978-3319544212.
“Advances in
Electronic Testing: Challenges and Methodologies”, D.Gizopoulos
(editor), Springer, January 2006, ISBN 0387294082 (link).
“Embedded
Processor-Based Self-Test”, D.Gizopoulos, A.Paschalis, Y.Zorian, Springer,
December 2004, ISBN 1-4020-2785-0 (link).
Graduated
PhD Students
George Xenoulis (now Atypon Systems)
Andreas Apostolakis
(now Nokia)
Nikos Foutris (now U Manchester)
Archimedes Pavlidis
(now U Piraeus)
Manolis Kaliorakis
(now European Dynamics)
Research
Support from Industry
AMD
– unrestricted research grant.
Cisco – unrestricted
research grant.
IBM
research – faculty award and shared university
research award.
Nvidia – equipment donation (graphics cards).
Intel – MARC
(Many-core Applications Research Community) – Test Scheduling in
Massively Parallel Architectures: Intel’s SCC – single chip cloud
computer.
AMD – equipment donation (workstations).
Sun/Oracle – equipment
donation (workstation).
Teaching
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University of Athens Computer Architecture I (undergraduate) (link to eclass) Computer Architecture II (undergraduate) (link to eclass) Advanced Computer Architecture (graduate) (link to eclass) |
Service
Program Committee Member (including):
IEEE
International Symposium on Performance Analysis of Systems and Software
(ISPASS), 2019.
ACM/IEEE
Design Automation Conference, (DAC), 2019, 2018.
IEEE International
Symposium on Workload Characterization (IISWC): 2017
ACM/IEEE International
Conference on Hardware/Software Codesign and System
Synthesis (CODES+ISSS): 2018, 2017, 2016.
IEEE International
Conference on Computer Design (ICCD): 2018, 2017, 2016.
IEEE International
Test Conference (ITC): 2018, 2017, 2016, 2014.
IEEE International
Test Conference Asia (ITC-Asia): 2017.
ACM International
Conference on Computing Frontiers (CF): 2015, 2014.
IEEE VLSI Test
Symposium (VTS): 2019, 2018, 2017, 2016, 2015, 2014, 2013, 2012, 2011, 2010,
2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002.
IEEE/IFIP
International Conference on Embedded and Ubiquitous Computing (EUC): 2016,
2015, 2014.
IEEE International
Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
(SAMOS), 2016, 2015, 2014, 2013, 2012.
IEEE/ACM Design,
Automation and Test in Europe Conference (DATE): 2016, 2012, 2011, 2010, 2009,
2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.
IEEE European Test
Symposium (ETS): 2017, 2016, 2015,
2014, 2013, 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002,
2001, 2000, 1999.
IEEE International
On-Line Testing Symposium (IOLTS): 2017, 2016, 2015, 2014, 2013, 2012, 2011,
2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.
IEEE Defect and Fault
Tolerance in VLSI Systems Symposium (DFTS): 2017, 2016, 2015, 2014, 2013, 2012,
2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.
IEEE Asian Test
Symposium (ATS): 2016, 2015, 2014, 2012, 2008.
IEEE Silicon Errors in
Logic – System Effects Workshop (SELSE): 2017, 2016, 2015, 2014.
ACM/IFIP International
Conference on VLSI-SoC (VLSI-SoC):
2010, 2009, 2008.
IEEE International
Workshop on Testing of Embedded Core-based Systems (TECS): 2002, 2001, 2000,
1999, 1998, 1997.
IEEE International
Workshop on Silicon Debug and Diagnosis (SDD): 2007, 2006, 2005.
IEEE International Symposium
on Design of Electronic Systems, Theory and Applications (DELTA): , 2008, 2006, 2004, 2002.
IEEE Latin American
Test Workshop (LATW): 2012, 2011, 2010, 2009, 2008, 2007.
HiPEAC Workshop on
Design for Reliability (DFR): 2013, 2012, 2011, 2010.
External Review Committee Member:
IEEE
International Symposium on High-Performance Computing (HPCA).
IEEE
International Symposium on Computer Architecture (ISCA).
General Chair
IEEE
International Symposium on Defect and Fault Tolerance (DFTS), October 2009,
Chicago, IL, USA.
IEEE
International On-Line Testing Symposium (IOLTS), July 2003, Kos, Greece.
IEEE
European Test Workshop (ETW), May 2002, Corfu, Greece.
IEEE Computer Society,
Test Technology Technical Council (TTTC), Tutorials and Education Group, 2005
– 2012.
Program Chair
IEEE International
On-Line Testing Symposium (IOLTS) 2019, 2018, 2017, 2016, 2015, 2014, 2013,
2012, 2011, 2010, 2009, 2008, 2007.
IEEE Workshop on
Silicon Errors in Logic – System Effects (SELSE) 2015, 2014.
IEEE International Workshop
on Design for Reliability and Variability (DRV), 2011
IEEE
International Symposium on Defect and Fault Tolerance (DFTS) 2008.
IEEE
International Workshop on Infrastructure Intellectual Property (IP), 2006,
2005, 2004, 2003.
IEEE Computer Society
TTTC, Test Technology Educational Program (TTEP), Tutorials Group, 2004, 2003,
2002, 2001, 2000.
Steering/Advisory Committee Member
IEEE International
Test Conference (ITC): 2004 – 2008.
IEEE European Test
Symposium – (ETS): 2001 – 2006 (chairman 2001 – 2003).
IEEE International
Symposium on Quality of Electronic Design (ISQED): 2000 – 2005.
Workshops Chair
IEEE International Symposium
on Microarchitecture (MICRO), Porto Alegre, Brazil ,
December 4-8, 2011.
Also:
Finance
Chair, Publicity Chair, Publications Chair, Tutorials Chair, Audio/Visual
Chair, Sponsors Chair, Regional Liaison
for several conferences.
Society
and Networks Membership
IEEE Fellow (Fellow:
2013, Senior member: 2003; Member: 1997; Student member: 1993).
IEEE
Computer Society Golden Core Member (since 2002).
ACM
Senior Member (2017).
HiPEAC Member.
Last update: May 2019.