Overview
The crucial problem facing today's high-speed microprocessors is
maintaining high processor utilization in the face of long
instruction and memory latencies. To alleviate this problem, modern
processors issue multiple instructions per cycle (i.e.,
superscalars), or interleave the execution of different threads in
different cycles (multithreaded processors). Ultimately, though,
both techniques are limited by the amount of parallelism available
within a single thread in a single cycle.
Simultaneous multithreading (SMT) is a technique that permits
multiple independent threads to issue instructions to a
superscalar's functional units in a single cycle. SMT combines the
multiple-instruction-issue features of wide superscalar processors
with the latency-hiding ability of multithreaded architectures. On
an SMT processor, all hardware contexts are active simultaneously,
competing each cycle for all available resources. This dynamic
sharing of processor resources enables SMT to exploit thread-level
and instruction-level parallelism interchangeably; both forms of
parallelism can be effectively used to increase processor
utilization.
Our studies have demonstrated that simultaneous multithreading
significantly improves processor throughput and performance on both
multiprogrammed and parallel workloads. We have shown that these
performance gains can be achieved in an architecture with only
minimal extensions to modern out-of-order superscalar
processors.
Our current and future work includes investigations of fast
synchronization techniques enabled by SMT. We are also conducting
research in other architectural and compiler issues for
simultaneous multithreading.
People
Publications
- Tuning Compiler Optimizations for Simultaneous
Multithreading (
Abstract, Postscript,
PDF)
Jack L. Lo,
Susan J.
Eggers, Henry
M. Levy, Sujay S. Parekh,
Dean M.
Tullsen
In 30th Annual International Symposium on Microarchitecture
(Micro-30), Dec. 1-3, 1997, p. 114-124.
- Software-Directed Register Deallocation for Simultaneous
Multithreaded Processors (
Abstract, Postscript,
PDF)
Jack L. Lo,
Sujay S.
Parekh, Susan J. Eggers, Henry M. Levy,
Dean M.
Tullsen
University of Washington Technical Report #UW-CSE-97-12-01,
December 1997.
- Simultaneous Multithreading: A Platform for Next-generation
Processors (PDF)
Susan J.
Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo,
Rebecca L. Stamm, and Dean M. Tullsen
IEEE Micro, September/October 1997, pages 12-18.
A version of this paper also appears as TR UW-CSE-97-04-02, April
1997.
- Converting Thread-Level Parallelism Into Instruction-Level
Parallelism via Simultaneous Multithreading (
Abstract,
Postscript,
PDF)
Jack L. Lo,
Susan J.
Eggers, Joel S. Emer, Henry M. Levy,
Rebecca L. Stamm, and Dean M. Tullsen
ACM Transactions on Computer Systems, August 1997, pages
322-354.
- Exploiting Choice: Instruction Fetch and Issue on an
Implementable Simultaneous Multithreading Processor (
Abstract, Postscript)
Dean M.
Tullsen, Susan J. Eggers,
Joel S. Emer, Henry M. Levy, Jack L. Lo, and
Rebecca L. Stamm
Proceedings of the 23rd Annual International Symposium on Computer
Architecture, Philadelphia, PA, May 1996, pages 191-202.
- Compilation Issues for a Simultaneous Multithreading
Processor (
Postscript)
Jack L. Lo,
Susan J.
Eggers, Henry
M. Levy, and Dean M. Tullsen
Proceedings of the First SUIF Compiler Workshop, Stanford, CA,
January 1996, p. 146-7.
- Simultaneous Multithreading: Maximizing On-Chip
Parallelism (
Abstract, Postscript)
Dean M.
Tullsen, Susan J. Eggers,
and Henry M.
Levy,
Proceedings of the 22rd Annual International Symposium on Computer
Architecture, Santa Margherita Ligure, Italy, June 1995, pages
392-403.
UW students:
Check the list of research projects still to do on the
student-affairs page.
This page maintained by Jack Lo
jlo@cs.washington.edu