Chaos Router Chip The Chaos Router
Chip is an implementation of the chaos routing algorithm in
hardware. It has been built and tested in 1.2 micron CMOS, and
redesigned in a 0.8 micron process for better performance.
Simulator The Chaos Router
Simulator is a powerful simulator which can simulate all sorts
of networks and routing algorithms. It includes a very nice graphical front end!
Standards for Presentation of Results At PCRCW '94, we discussed the presentation of
simulation results for routing algorithms. We were able to come up
with some guidelines for
presentation of results.
Other Research Groups We're building a list of all research groups that have webs describing research
in routing and/or interconnection networks.
Parallel Computer Routing and Communication Workshop (PCRCW)
'94 PCRCW '94 was held at the Univeristy of Washington in Seattle
in May 1994. Proceedings are available
now.