(System Python)

The main objective of my PhD thesis was the development of a software tool for SoC (System on Chip) design, called SysPy (System Python). SysPy focuses on the design of processor-centric systems, where a microprocessor can easily handle all communication tasks between the different hardware components integrated into a SoC.

To increase design productivity there is a lot of interest, both in academia and the industry, in developing tools that can help the designers capture high level hw/sw descriptions of SoCs. Such tools should support flexible hw/sw partitioning and component reuse, thus facilitating exploitation of existing domain-specific IP cores repositories, supported and optimized by third parties.

In order to develop a "glue software" which would adequately describe both the hardware and the software aspects of an embedded SoC, we decided to use Python, a high level scripting language with fast growing popularity among software engineers, that supports both structured and object-oriented programming. Let's summarize the main Python features that justify its use for what we have attempted: (i) The language has very clean and simple syntax. (ii) A large variety of complex data types is supported. (iii) Python supports dynamic typing, no variable declaration is needed. (iv) C/C++ functions can be imported and used and also tools exist for parsing Python-to-C code. (v) A plethora of Python related tools are available in the public domain.

We have developed a SoCs design tool that can be used to:

(i) Describe new hardware components in Python and translate them to high quality synthesizable VHDL code.

(ii) Create system-level processor-centric SoC descriptions that are formed by flexibly combining:
Hardware components described in Python that the tool will translate into VHDL.

Available third party VHDL components from commercial libraries.

Pre-synthesized netlist files of arithmetic or other components for specific FPGA devices.

Processor cores with the appropriate software supplied as an external C file.

(iii) Support O/S Linux based software running on the processor core (Leon3).

(iv) Support high-level sw/hw co-verification of a design using Python descriptions, early in the design phase.

SysPy supports popular 32-bit processor architectures such as OpenRisc and Leon and an 8-bit architecture core of the popular AVR ATmega128.

To demonstrate the capabilities of our tool, we have used SysPy to design a processor-centric SoC system that applies Sobel edge detection to grayscale images. More information about this system can be found here.

Another complete SoC system has been developed that performs simulations of biochemical reaction networks (BioModels) using Gillespie’s Stochastic Simulator Algorithm (SSA). More information about this system can be found here.

To demonstrate the design flow of a complete embedded SoC with the usage of a Linux operating system, we desinged and implemented in a Virtex-5 FPGA, a SoC for genre classification of music, wav format, music files. More information about this system can be found here.

In SysPy a git repository is used for version control. The repository is hosted in GitHub, which is the largest and most popular online code repository. Further information on how to checkout the repository and start working with SysPy
can be found in:
https://github.com/evlog/SysPy

List of publications (for the SysPy project):

E. Logaras, E. Koutsouradis and E.S. Manolakos. "Python facilitates the rapid prototyping and hw/sw verification of processor centric SoCs for FPGAs",
accepted for lecture presentation to the IEEE International Symposium on Circuits and Systems (ISCAS), May 2016.

E. Logaras, O. G. Hazapis, and E. S. Manolakos, "Python to accelerate embedded SoC design: a case study for systems biology",
ACM Transactions on Embedded Computing Systems, vol. 13, no. 4, pp. 84:1 - 84:25, February, 2014 pdf

This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in ACM TECS,
http://dx.doi.org/10.1145/2560032)

O. G. Hazapis, E. Logaras and E. S. Manolakos, "A soft IP core generating SoCs for the efficient stochastic simulation of large Biomolecular Networks using FPGAs",
in Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2012, pp. 77-80.

E. Logaras and E. S. Manolakos, "SysPy: using Python for processor-centric SoC design",
in Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2010, pp. 764-767.

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